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mosel vitelic 1 V53C518165A 1m x 16 edo page mode cmos dynamic ram optional self refresh V53C518165A rev. 1.1 january 1998 high performance 50 60 max. ras access time, (t rac ) 50 ns 60 ns max. column address access time, (t caa ) 25 ns 30 ns min. extended data out page mode cycle time, (t pc ) 20 ns 25 ns min. read/write cycle time, (t rc ) 84 ns 104 ns features n 1mb x 16-bit organization n edo page mode for a sustained data rate of 50 mhz n ras access time: 50, 60 ns n dual cas inputs n low power dissipation n read-modify-write, ras -only refresh, cas -before-ras refresh refresh interval: 1024 cycles/16 ms n available in 42-pin 400 mil soj and 44/50-pin 400 mil tsop-ii packages n single 5v 10% power supply n ttl interface n optional self refresh (V53C518165As) refresh interval: 1024 cycles/128 ms description the V53C518165A is a 1048576 x 16 bit high- performance cmos dynamic random access memory. the V53C518165A offers page mode op- eration with extended data output. the V53C518165A has symmetric address, 10-bit row and 10-bit column. all inputs are ttl compatible. edo page mode operation allows random access up to 1024 x 16 bits, within a page, with cycle times as short as 20ns. these features make the V53C518165A ideally suited for a wide variety of high performance com- puter systems and peripheral applications. device usage chart operating temperature range package outline access time (ns) power temperature mark k t 50 60 std. 0 c to 70 c blank ?0 c to +85 c i
2 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A pin names a 0 ? 9 row, column address inputs ras row address strobe ucas column address strobe/upper byte control lcas column address strobe/lower byte control we write enable oe output enable i/o 1 ?/o 16 data input, output v cc +5v supply v ss 0v supply nc no connect description pkg. pin count tsop-ii t 44/50 soj k 42 v cc i/o 1 i/o 2 i/o 3 i/o 4 v cc i/o 5 i/o 6 i/o 7 i/o 8 nc nc we ras nc nc a 0 a 1 a 2 a 3 v cc v ss i/o 16 i/o 15 i/o 14 i/o 13 v ss i/o 12 i/o 11 i/o 10 i/o 9 nc lcas ucas oe a 9 a 8 a 7 a 6 a 5 a 4 v ss 5 6 7 8 9 10 11 12 1 2 3 4 40 39 38 37 36 35 34 33 32 31 30 29 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 42 21 41 v cc i/o 1 i/o 2 i/o 3 i/o 4 v cc i/o 5 i/o 6 i/o 7 i/o 8 nc nc nc we ras nc nc a 0 a 1 a 2 a 3 v cc v ss i/o 16 i/o 15 i/o 14 i/o 13 v ss i/o 12 i/o 11 i/o 10 i/o 9 nc nc lcas ucas oe a 9 a 8 a 7 a 6 a 5 a 4 v ss 5 6 7 8 9 10 11 1 2 3 4 15 16 17 18 19 20 511816500-02 21 22 23 24 25 46 45 44 43 42 41 40 50 49 48 47 36 35 34 33 32 31 30 29 28 27 26 42-pin plastic soj pin configuration top view 44/50-pin plastic tsop-ii pin configuration top view
3 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A block diagram no . 2 cloc k gener ator data in buff er data out buff er column address buff ers (10) refresh controller ro w decoder refresh counter (10) v oltage do wn gener ator no . 1 cloc k gener ator ro w address buff ers (10) 10 16 i/o1 i/o2 i/o16 16 vcc vcc (inter nal) oe 10 10 10 16 1024 1024 x16 memor y arr a y 1024 x 1024 x 16 sense amplifier i/o gating 316516500-03 column decoder a0 ucas we lcas a1 a2 a3 a4 a5 a6 a7 a8 a9 ras 10 ?? absolute maximum ratings* * note: stresses greater than those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance* t a = 25 c, v cc = 5 v 10%, v ss = 0 v, f = 1 mhz * note: capacitance is sampled and not 100% tested. symbol parameter commercial extended units v n power supply voltage -1 to +7 -1 to +7 v v dq input/output voltage -0.5 to min (v cc +0.5, 7.0) -0.5 to min (v cc +0.5, 7.0) v t bias temperature under bias -10 to +125 -65 to +135 c t stg storage temperature -55 to +125 -65 to +150 c symbol parameter min. max. unit c in1 address input 5 pf c in2 ras , ucas , lcas , we , oe 7 pf c out data input/output 7 pf
4 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A dc and operating characteristics (1-2) t a = 0 c to 70 c, v cc = 5 v 10%, v ss = 0 v, t t = 2ns, unless otherwise specified. symbol parameter access time commercial extended unit test conditions notes min. max. min. max. i li input leakage current (any input pin) ?0 10 ?0 10 m a v ss v in v cc + 0.5v 1 i lo output leakage current (for high-z state) ?0 10 ?0 10 m a v ss v out v cc + 0.5v ras , cas at v ih 1 i cc1 v cc supply current, operating 50 130 200 ma t rc = t rc (min.) 2, 3, 4 60 115 180 i cc2 v cc supply current, ttl standby 2 2 ma ras , cas at v ih other inputs 3 v ss i cc3 v cc supply current, ras -only refresh 50 130 200 ma t rc = t rc (min.) 2, 4 60 115 180 i cc4 v cc supply current, edo page mode operation 50 50 90 ma minimum cycle 2, 3, 4 60 40 75 i cc5 v cc supply current, during cas -before- ras refresh 50 130 200 ma t rc = t rc (min.) 2, 4 60 115 180 i cc6 v cc supply current, cmos standby 1.0 1.0 ma ras 3 v cc ?0.2 v, cas 3 v cc ?0.2 v other input 3 v ss 1 i cc7 self refresh (optional) 250 250 m a cbr cycle with t ras 3 t rass (min.) , cas held low, we = v cc -0.2v, address and d in = v cc -0.2v or 0.2v v cc power supply voltage 4.5 5.5 4.5 5.5 v v il input low voltage ?.5 0.8 ?.5 0.8 v 1 v ih input high voltage 2.4 v cc +0.5 2.4 v cc +0.5 v 1 v ol output low voltage 0.4 0.4 v i ol = 4.2 ma 1 v oh output high voltage 2.4 2.4 v i oh = ?.0 ma 1
5 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A ac characteristics (5,6) t a = 0 c to 70 c, v cc = 5 v 10%, t t = 2ns, unless otherwise noted # symbol parameter limit values unit note -50 -60 min. max. min. max. common parameters 1 t rc random read or write cycle time 84 104 ns 2 t rp ras precharge time 30 40 ns 3 t ras ras pulse width 50 10k 60 10k ns 4 t cas cas pulse width 8 10k 10 10k ns 5 t asr row address setup time 0 0 ns 6 t rah row address hold time 8 10 ns 7 t asc column address setup time 0 0 ns 8 t cah column address hold time 8 10 ns 9 t rcd ras to cas delay time 12 37 14 45 ns 10 t rad ras to column address delay 10 25 12 30 ns 11 t rsh ras hold time 13 15 ns 12 t csh cas hold time 40 50 ns 13 t crp cas to ras precharge time 5 5 ns 14 t t transition time (rise and fall) 1 50 1 50 ns 7 15 t ref refresh period 16 16 ms read cycle 16 t rac access time from ras 50 60 ns 8, 9 17 t cac access time from cas 13 15 ns 8, 9 18 t caa access time from column address 25 30 ns 8,10 19 t oac oe access time 13 15 ns 20 t car column address to ras lead time 25 30 ns 21 t rcs read command setup time 0 0 ns 22 t rch read command hold time 0 0 ns 11 23 t rrh read command hold time referenced to ras 0 0 ns 11 24 t clz cas to output in low-z 0 0 ns 8 25 t off output buffer turn-off delay 0 13 0 15 ns 12 26 t oez output turn-off delay from oe 0 13 0 15 ns 12 27 t dzc data to cas low delay 0 0 ns 13 28 t dzo data to oe low delay 0 0 ns 13 29 t cdd cas high to data delay 10 13 ns 14 30 t odd oe high to data delay 10 13 ns 14
6 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A write cycle 31 t wch write command hold time 8 10 ns 32 t wp write command pulse width 8 10 ns 33 t wcs write command setup time 0 0 ns 15 34 t rwl write command to ras lead time 8 10 ns 35 t cwl write command to cas lead time 8 10 ns 36 t ds data setup time 0 0 ns 16 37 t dh data hold time 8 10 ns 16 read-modify-write cycle 38 t rwc read-write cycle time 113 138 ns 39 t rwd ras to we delay time 64 77 ns 15 40 t cwd cas to we delay time 27 32 ns 15 41 t awd column address to we delay time 39 47 ns 15 42 t oeh oe command hold time 10 13 ns edo page mode cycle 43 t hpc edo page mode cycle time 20 25 ns 44 t cp cas precharge time 8 10 ns 45 t cpa access time from cas precharge 27 32 ns 7 46 t coh output data hold time 5 5 ns 47 t rasp ras pulse width in edo page mode 50 200k 60 200k ns 48 t rhpc cas precharge to ras delay 27 32 ns 49 t oes oe setup time prior to cas 5 5 ns edo page mode read-modify-write cycle 50 t prwc edo page mode read-write cycle time 58 68 ns 51 t cpwd cas precharge to we 41 49 ns cas -before- ras refresh cycle 52 t csr cas setup time 10 10 ns 53 t chr cas hold time 10 10 ns 54 t rpc ras to cas precharge time 5 5 ns 55 t wrp write to ras precharge time 10 10 ns 56 t wrh write hold time referenced to ras 10 10 ns cas -before- ras counter test cycle 57 t cpt cas precharge time ( cas -before- ras counter test cycle) 35 40 ns # symbol parameter limit values unit note -50 -60 min. max. min. max. ac characteristics (cont?)
7 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A optional self refresh 58 t ref self refresh period 128 128 ms 59 t rass ras pulse width 100k 100k ns 17 60 t rps ras precharge time 95 110 ns 17 61 t chs cas hold time -50 -50 ns 17 # symbol parameter limit values unit note -50 -60 min. max. min. max.
8 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A notes: 1. all voltage are referenced to v ss . 2. i cc1 , i cc3 , i cc4 , and i cc5 depend on cycle rate. 3. i cc1 and i cc4 depend on output loading. specified values are measured with the output open. 4. address can be changed once or less while ras = v il . in the case of i cc4 it can be changed once or less during an edo page mode cycle. 5. an initial pause of 200 m s is required after power-up followed by 8 ras cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas -before- ras initialization cycles instead of 8 ras cycles are required. 6. ac measurements assume t t = 2ns. 7. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. transition times are also measured between v ih and v il . 8. measured with the specified current load and 100pf at v ol = 0.8 v and v oh = 2.0 v. access time is determined by the latter of t rac , t cac , t caa , t cpa , t oac , t cac is measured from tristate. 9. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 10. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t caa . 11. either t rch or t rrh must be satisfied for a read cycle. 12. t off (max.) , t oez (max.) define the time at which the outputs acheive the open-circuit condition and are not referenced to output voltage levels. t off is referenced from the rising edge of ras or cas , whichever occurs last. 13. either t dzc or t dzo must be satisfied. 14. either t cdd or t odd must be satisfied. 15. t wcs , t rwd , t cwd , and t awd are not restrictive operating parameters. they are included in the data sheet as electri- cal characteristics only. if t wcs > t wcs (min.) , the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if t rwd > t rwd (min.) , t cwd > t cwd (min.) , and t awd > t awd (min.), the cycle is a read-write cycle and i/o pins will contain data read from the selected cells. if neither of the above sets of con- ditions is satisfied, the condition of the i/o pins (at access time) is indeterminate. 16. these parameters are referenced to the cas leading edge in early write cycles and to the we leading edge in read-write cycles. 17. when using self refresh mode, the following refresh operations must be performed to ensure proper dram oper- ation: if row addresses are being refreshed on an evenly distributed manner over the refresh interval using cbr refresh cycles, then only one cbr cycle must be performed immediately after exit from self refresh. if row addresses are being refreshed in any other manner (ror - distributed/burst; or cbr-burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from self refresh.
9 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A waveforms of read cycle row column row valid data out ras ucas address we oe i/o (inputs) i/o (outputs) v ih v il t ras t rc t csh t rad t cas t rp t rah t crp t rsh t rcd t car t asr t cah t asc t asr t rch t rrh t rcs t caa t oac t clz t cac t oez t odd t cdd t off t dzc t dzo t rac hi z hi z ?? or ? 511816502-04 v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol lcas
10 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A waveforms of write cycle (early write) ras address we oe i/o (inputs) i/o (outputs) . t ras valid data in hi z column row row ?? or ? 511816502-05 t rc t rp t csh t rcd t rsh t cas t crp t car t rad t asr t asc t cah t asr t cwl t rah t wcs t wp t wch t rwl t dh t ds v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol ucas lcas
11 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A waveforms of write cycle ( oe controlled write) valid data t rwl t wp t oeh t cwl row ?? or ? hi-z hi-z column row t asc t rad t car t cah t rah ras address we oe i/o (inputs) i/o (outputs) t cas t rsh t rcd t asr t asr 511816502-06 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il t rc t ras t rp t csh t crp t odd t dzo t dzc t dh t ds t oez t clz t oac ucas lcas
12 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A waveforms of read-write (read-modify-write) cycle row row t rwc i/o (outputs) i/o (inputs) oe we column valid data in data out t rac ?? or ? ras address 511816502 -07 v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ol v oh t ras t rp t csh t rcd t rsh t cas t crp t asr t cah t asc t rah t asr t rad t awd t cwd t rwd t cwl t rwl t wp t oeh t caa t oac t rcs t ds t dh t dzo t dzc t clz t cac t odd t oez ucas lcas
13 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A waveforms of edo page mode read cycle t rp column 2 row data out ras i/o we address v ih v il ?? or ? oe t rasp (output) data out column n column 1 data out 1 2 n 511816502-08 v ih v il v ih v il v ih v il v oh v ol v ih v il t rhpc t rcd t crp t pc t cas t cp t cas t rsh t cas t crp t csh t car t asr t rah t asc t cah t asc t cah t asc t cah t rad t rcs t rrh t rch t cac t caa t cpa t oes t cpa t caa t off t oac t rac t cac t caa t clz t coh t coh t oez t cac ucas lcas
14 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A waveforms of edo page mode read cycle ( oe control) column 2 row data out ras i/o we address ?? or ? oe t rasp (output) data out column n column 1 data out 1 2 n 511816502 -09 v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t rcd t rhpc t rp t crp t rsh t cas t cas t cp t cas t pc t crp t csh t car t asr t rah t asc t cah t asc t cah t asc t cah t rad t rcs t rrh t rch t cac t cac t caa t caa t cpa t cpa t oes t off t oehc t oehc t oac t oez t oac t oep t oez t oac t oep t oez t cac t caa t rac t clz ucas lcas
15 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A waveforms of edo page mode read cycle ( we control) column 2 row data out ras i/o we address ?? or ? oe t rasp (output) data out column n column 1 data out 1 2 n 511816502-10 v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t rp t rcd t rhpc t pc t crp t cas t cp t cas t rsh t cas t crp t csh t asr t rah t asc t cah t asc t cah t asc t cah t car t rad t caa t caa t rrh t rch t rcs t rch t rcs t rch t rcs t wpz t oes t oac t cpa t cac t cpa t cac t off t oez t wez t wez t cac t clz t caa t car t wpz ucas lcas
16 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A waveforms of edo page mode early write cycle column 1 column 2 row addr data in n data in 2 data in 1 column n ras i/o (input) we address ?? or ? oe t rasp 511816502-11 v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t rcd t rhpc t rp t crp t pc t cas t cp t cas t cas t crp t rsh t car t cah t asc t cah t asc t cah t csh t asc t rah t asr t rad t cwl t wch t wp t wcs t wp t wp t wch t wch t wcs t wcs t cwl t cwl t rwl t ds t dh t dh t ds t dh t ds ucas lcas
17 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A waveforms of edo page mode late write cycle column 2 row data in ras i/o we address ?? or ? oe (input) data in column n column 1 data in 1 2 n 511816502-12 v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t rasp t rcd t rp t crp t pc t cas t cp t cas t cp t cas t rsh t crp t csh t rah t asr t asc t cah t cah t cah t asc t asc t car t rad t cwl t cwl t cwl t rwl t rcs t rcs t rcs t wp t wp t wp t oeh t oeh t oeh t odd t odd t ds t dh t ds t dh t ds t dh t odd ucas lcas
18 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A waveforms of edo page mode read-modify-write cycle ras we oe address i/o (inputs) i/o (outputs) data in data in data in data out out data data out row column column row column t rasp v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t prwc t csh t rcd t cas t cas t cas t rsh t rp t crp t asr t car t cah t asc t cah t cp t cah t asc t rad t rah t asr t rwl t cwl t cpwd t cwd t cwl t cwd t cpwd t cwl t cwd t rwd t rcs t awd t caa t oac t awd t oac t wp t wp t awd t wp t rac t dzo t cac t dzc t clz t odd t oez t ds t dh t oeh t dzc t cpa t caa t clz t odd t oez t ds t dh t dzc t cpa t clz t oeh t cac t caa t ds t dh t oeh t odd t oez ucas lcas t asc t oac 511816502-13
19 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A waveforms of ras only refresh cycle row row hi-z address ras i/o (outputs) ?? or ? v ih v il v ih v il v ih v il v oh v ol t rc t ras t rp t crp t rpc t asr t asr t rah ucas lcas 511816502-14
20 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A waveforms of cas -before- ras refresh cycle t rc hi-z ?? or ? ras i/o (outputs) i/o (inputs) oe we v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rp t rp t rpc t csr t cp t chr t rpc t crp t wrp t wrh t oez t cdd t odd t off ucas lcas 511816502-15
21 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A waveforms of cas -before- ras self refresh cycle (optional) hi-z ?? or ? ras i/o (outputs) i/o (inputs) oe we v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t rass t rps t rp t rpc t csr t cp t chs t crp t wrp t wrh t oez t cdd t odd t off ucas lcas 511816502-15
22 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A waveforms of hidden refresh read cycle ras i/o (outputs) i/o (inputs) oe we address ?? or ? valid data out row column row hi-z 511816502-16 v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t rc t rc t ras t rp t ras t rp t rcd t rsh t chr t crp t rad t asc t rah t asr t cah t wrp t wrh t asr t rrh t rcs t caa t oac t dzc t dzo t cdd t odd t off t oez t cac t clz t rac ucas lcas
23 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A waveforms of hidden refresh early write cycle ras i/o (output) i/o (input) we address ?? or ? t rc row row valid data hi-z column v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rp t rcd t rsh t rc t ras t rp t crp t chr t rad t rah t asr t asc t cah t asr t wcs t wch t wp t wrp t wrh t ds t dh ucas lcas 511816502-17
24 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A notes:
25 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A notes:
26 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A notes:
27 V53C518165A re v . 1.1 j an uar y 1998 mosel vitelic V53C518165A package diagrams 42-pin 400 mil soj 44/50-pin 400 mil tsop-ii 1.08 ?.010 [27.41 ?.25 ] 0.05 [1.27] 1.0 [25.4] 0.017 0.004 [0.43 0.1] 0.004 [0.1] 0.045 [1.15] min 0.145 [3.68] max .406 ?.012 [10.3 ?.3 ] .441 0.006 [11.2 0.15 ] 42 1 22 21 0.370 0.010 [9.4 0.25] .406 ?.012 (1) [10.3 ?0.3] .441 ?.006 [11.2 ?.15 ] (1) 0.2 unit in inches [mm] 0.81 [.032] max +0.12 ?.05 0.008 +0.005 ?.002 0.088 0.004 [2.24 0.1] (1) does not include plastic or metal protrusion of 0.010 [0.25] max per side. 50 26 36 40 1 25 15 11 0.016 +0.002 ?.004 0.4 +0.05 ?.1 0.006 +0.003 ?.001 0.15 +0.08 ?.03 0.008 [0.2] 44x m unit in inches [mm] 0.004 0.002 [0.1 0.05] 0.031 [0.8] 0.039 0.002 [1 0.05] 0.4 0.005 [10.16 0.13] 0.463 0.008 [11.76 0.2] 0.047 max [1.2 max] 0.004 [0.1] 0.825 0.005 [20.95 0.13] does not include plastic or metal protrusion of 0.010 [0.25] max. per side 1 1 0.020 0.004 [0.5 0.1]
mosel vitelic w orld wide offices V53C518165A u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 011-852-665-4883 fax: 011-852-664-7535 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 011-886-2-545-1213 fax: 011-886-2-545-1209 1 creation road i science based ind. park hsin chu, taiwan, r.o.c. phone: 011-886-35-783344 fax: 011-886-35-792838 japan wbg marine west 25f 6, nakase 2-chome mihama-ku, chiba-shi chiba 261-71 phone: 011-81-43-299-6000 fax: 011-81-43-299-6555 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 southwestern suite 200 5150 e. pacific coast hwy. long beach, ca 90804 phone: 562-498-3314 fax: 562-597-2174 central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. ?cop yr ight 1998, mosel vitelic inc. 1/98 pr inted in u .s .a. mosel vitelic 3910 n. first street, san jose , ca 95134-1501 ph: (408) 433-6000 f ax: (408) 433-0952 tlx: 371-9461 u .s. sales offices

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